16 bit; 32-bit application; 3DNow!; 3DNow! Professional; 64 bit; Adaline; address space; ANSI/SPARC Architecture; architecture; array; asynchronous; asynchronous logic; Axiomatic Architecture Description Language; big-endian; bit slice; BLOB; bus; bus master; Byzantine; CA; Cache On A STick; CAM; cellular multiprocessing; Cellular Neural Network; central processing unit; CNN; cognitive architecture; Core Protocol Stack; CPU; DAG; Data Address Generator; data bus; data path; direct mapped cache; Direct Memory Access; distributed memory; DNA computing; Dynamic Address Translation; dynamic translation; emulation; -endian; ESA; Extended Industry-Standard Architecture; fault; fault tolerance; fetch-execute cycle; first generation computer; flat address space; Flynn's taxonomy; fourth generation computer; HCF; hit; hit rate; Industry Standard Architecture; input; instruction prefetch; instruction set; instruction set architecture; Intelligent Input/Output; ISA; Java Virtual Machine; Lisp Machine; little-endian; main memory; memory address space; memory mapped I/O; Memory Type Range Registers; Micro Channel Architecture; microprocessor; middle-endian; Moore's Law; net; Next Program Counter; Non-Uniform Memory Access; northbridge; NPC; NUXI problem; orthogonal instruction set; output; PE; ping-pong; pipeline; pipeline break; PNP; PowerPC Platform; power save mode; prepaging; primary cache; Redundant Arrays of Independent Disks; scalar; second generation computer; segmented address space; set associative cache; single program/multiple data; southbridge; SSE-2; stack pointer; state; Streaming SIMD Extensions; superscalar; systolic array; Task Control Block; third generation computer; three-tier; Translation Look-aside Buffer; USB; Very Large Memory; virtual; virtual address; VLM; von Neumann architecture; wait state; Windows Open Service Architecture; wintel; working set; write-through; XT bus architecture;